To accomplish a timing synchronization circuit which is capable of accomplishing characteristics, applicable to multi-level QAM and with simple configuration, even if a clock oscillator of which the frequency stability is not so high, is used.

In the timing synchronizing circuit, comprising a timing error detection circuit and a timing correction circuit, a sample number (k) is counted and timing error estimates θ1(k1), θ1(k2); when the sample number becomes k1, k2 (0<k1<k2), θ1(k1) is subtracted from θ1(k2); when the sample number becomes K2, a subtraction output [θ1(k2)-θ1(k1)] is divided with a setting value [k2-k1], a division output [(θ1(k2)-θ1(k1))/(k2-k1)] is multiplied by the sample number (k); the timing error estimate θ1(k) and a multiplication output [((θ1(k2)-θ1(k1))/(k2-k1))k] are added; and a result is given to the timing correction circuit as a timing error estimate θ2(k), which takes a clock frequency error into account.