PURPOSE: To increase a data transmitting margin and to prevent malfunctions by inputting a clock signal assigning the output signal from a switching means and the completion of data transmission and providing with a latch means outputting a clock signal being a master clock inside a tip.

CONSTITUTION: When a first clock signal CLK1 is in a H state, since a signal in a L state is outputted with a fourth NOR gate NO4, a second clock signal CLK2 outputted from a third NOR gate NO3 becomes inverted signal to the output signal of a second inverter 12 and becomes L state. Next, when the signal CLK1 is transited to the L state, the signal in the H state is outputted with the gate NO4. In this case, since the signal CLK2 is maintained in the L state regardless of the state of a signal RAS, the active state of the signal CLK2 becomes longer than the signal RAS. By this way, a data transmitting time between dual ports is compensated, the transmitting margin becomes large, and also the data transmission is correctly executed in a prescribed time.