Title:
MASTER SLICE INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS5940547
Kind Code:
A
Abstract:
PURPOSE:To improve the reliability of an operation by a method wherein all unused cells in a master slice are connected in the status under a specified potential. CONSTITUTION:A connector 6c connecting to a lead wire 6a connected to a power supply voltage is extended commonly connecting to respective N type conductive diffused regions 5a-5c through the intermediary of the contacts 7d- 7f. On the other hand, another connector 6d is extended from another lead wire 6b connected to an earth potential respectively connecting to the P type diffused regions 3a-3c through the intermediary of the contacts 7a-7c. Besides the other connector 6e connected to the lead wire 6b is provided to cover almost overall N-MOS regions respectively connecting to the gate electrodes 4a, 4b through the intermediary of the contacts 7g, 7h. Furthermore a conductor 6f connected to the lead wire 6a is provided to cover the P-MOS part of the diffused regions as much as possible. In such a constitution, relatively large capacity may be available protecting the diffused regions from external electromagnetic and inductive disturbances.
Inventors:
SETO TOSHIO
Application Number:
JP14913482A
Publication Date:
March 06, 1984
Filing Date:
August 30, 1982
Export Citation:
Assignee:
RICOH KK
International Classes:
H01L27/092; H01L21/82; H01L21/8238; H01L27/118; (IPC1-7): H01L27/08
Attorney, Agent or Firm:
Masaaki Kobashi
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