PURPOSE: To decrease the number of input signals to an instruction decoder, and to facilitate the IC-implementation of a data processor, by setting the execution cycle of the decoding of instruction words according to the number of words, and providing an FF for controlling the decoding of each word.

CONSTITUTION: Instruction words are stored in the memory 11 of a data processor, and instruction words having word length preset according to a control signal such as an address signal that a control circuit generates are read out of the memory 11, word by word. Those read instruction words are stored in an instruction register 12, and those stored instruction words are decoded by an instruction decoder 13 to generate various control signals C1WCn which correspond to the instruction words. When the instruction word read out of the memory 11 is plural, information 1 is stored in an FF14. The decoding of every word is controlled by the FF14 to decrease the number of input signals to the decoder 13, and thus the chip area and the number of elements of the data processor are decreased to facilitate the IC-implementation of the processor.