Title:
【発明の名称】加算回路
Document Type and Number:
Japanese Patent JP2607538
Kind Code:
B2
Abstract:
A binary digital full adder as a component element of a digital circuit receives three binary signals including two input signals and a carry-in from the lower digit. The adder comprises a four-state logic converter for adding together the three binary signals in terms of current addition to convert the sum into a four-state logic signal, and an encoder for deciding a four-state logic level to encode it into a binary sum and a carry-out.
Inventors:
Toshihiko Shimizu
Hotao Masao
Hotao Masao
Application Number:
JP21274687A
Publication Date:
May 07, 1997
Filing Date:
August 28, 1987
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
G06G7/14; G06F7/50; G06F7/501; G06F7/503; G06F7/506; G06J1/00; (IPC1-7): G06F7/50
Domestic Patent References:
| JP58114237A | ||||
| JP58114238A | ||||
| JP58144258A |
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)