PURPOSE: To stabilize synchronous demodulation reproducing by providing an M frame synchronism detecting means which detects the continuance of a frame synchronizing pattern for M frames and an M frame buffer storage means.

CONSTITUTION: A frame synchronism detecting circuit 1 which detects the continuance of the frame synchronizing pattern for a predetermined number M of frames (M is an integer equal to or larger than 2) instead of a conventional frame synchronism detecting circuit, a frame buffer memory 4 to store an M-frame portion of bit stream data, the same descramble generator 2 as conventional, a control code detector 3, a bit deinterleaver 5, an error detecting and correcting circuit 6, a range processing circuit 7, and an interpolating muting circuit 8 are provided to constitute a frame synchronism reproducing circuit. An M-frame portion of data stored in the M frame buffer memory 4 is used to perform the PCM demodulation processing for the period of time from establishment of M-frame synchronism to that of M-frame continuous asynchronism.