PURPOSE: To perform high-speed AD conversion by providing a comparator which generates a selector signal in response to outputs of respective stages of an analog shift register, and supplying a binary signal, selected by said selector signal, to a digital shift register.

CONSTITUTION: Outputs of respective stages 11∼1n of an analog shift register 1 are compared with reference values at respective stages of a comparator 2 to obtain a binary selector signal, which is coupled with respective stages of a digital shift register 3. According to whether the selector signal is 1 or 0, the digital shift register 3 selects and stores the contents of the register 3 or the binary code of a binary code generator 4. Consequently, successive analog inputs Ain are AD-converted precisely at a high speed.