PURPOSE: To prevent read data from being absent as to the elastic memory circuit which is used for a mobile communication system using, for example, a TDMA system.
CONSTITUTION: The elastic memory circuit which has a write address generating means 2 and a memory means 1 is provided with a synchronizing signal detecting means 3 which sends out a synchronism detection signal when detecting a synchronizing signal in input data, a load timing generating means 4 which delays the inputted synchronism detection signal by a half as many as write addresses from the input point of time by using a read clock and then sends it out as a read load timing signal, and a read address generating means 5 which sends out the address, obtained by adding a half of the number of write address to the write address at the time of the application of the read load timing among inputted write address, to the memory means as a read address.
JPH0212326 | DISK CONTROLLER |
JPS51131228 | DEVICE FOR PROCESSING DIGITAL INFORMATION ELEMENT |
JPH06176561 | PARALLEL DIFFERENCE FLAG LOGIC |