PURPOSE: To prevent the saturation of a transistor(TR) which is caused at an undershoot time, by adding a level clamping circuit using the TR to suppress the undershoot.

CONSTITUTION: Level clamping TRs Q11 and Q12 and a terminal VC which drives their base potentials are added. By these TRs Q11 and Q12, potentials at nodes C1 and C2 have levels clamped to values which are lower than the potential of the terminal VC by values corresponding to forward voltages VBE between bases and emitters of TRs Q11 and Q12. Therefore, when the potential which is higher than desired low potentials of nodes C1 and C2 by the voltage VBE is supplied to the terminal VC, signal waveforms of nodes C1 and C2 at a transition time are clamped to desired potentials, and a signal of no undershoot is attained. Consequently, the saturation of the TR caused at the undershot time is prevented.