Title:
SEMICONDUCTOR DEVICE AND ITS MANUFACTURE
Document Type and Number:
Japanese Patent JPH0799171
Kind Code:
A
Abstract:
PURPOSE: To provide a manufacturing method, of a MOS transistor, which can reduce a sheet resistance without casuing a bridge.
CONSTITUTION: The manufacture is provided with a process which forms a gate electrode 6 on a silicon substrate 1, with a process which forms a source diffused layer 13a and a drain diffused layer 13b after that, with a process which deposites a Ti film 14 on the whole face and which forms TiSi2 layers 15a, 15b by a heat treatment and with a process which selectively removes unreacted Ti and Ti compounds other than TiSi2 by using a mixed solution (H2O2:H2SO4=1:1) of hydrogen water and sulfuric acid.
Inventors:
MORIMOTO TOYOTA
ARAI HIDEAKI
ARAI HIDEAKI
Application Number:
JP24256193A
Publication Date:
April 11, 1995
Filing Date:
September 29, 1993
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
H01L21/28; H01L21/308; H01L21/336; H01L29/78; (IPC1-7): H01L21/28; H01L21/308; H01L21/336; H01L29/78
Attorney, Agent or Firm:
Takehiko Suzue
Next Patent: LATTICE ARRANGEMENT FOR MASKING TAPE PROCESS