Title:
【発明の名称】2進デ-タ符号化及び復号化方式
Document Type and Number:
Japanese Patent JPH07118657
Kind Code:
B2
Abstract:
A binary data encoding process comprises the steps of separating a given binary data sequence at every two bits by a serial/parallel shift register (18), and converting the separated 2-bit data into a 3-bit code by using a logic circuit (19) and a parallel/serial shift register (20). A conversion pattern in the logic circuit (19) is exclusively determined based on the 2-bit data to be converted, 1-bit data immediately before and 2-bit data immediately after said 2-bit data, and a 3-bit code converted immediately before the conversion of said 2-bit data, wherein a succession of at least one but no more than seven "0" exists between an arbitrary "1" and the succeeding "1" in the converted 3-bit code sequence.
Inventors:
Teruo Furukawa
Minoru Ozaki
Minoru Ozaki
Application Number:
JP7851485A
Publication Date:
December 18, 1995
Filing Date:
April 15, 1985
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
G11B20/14; H03M5/12; H03M5/14; H03M7/14; H03M13/00; (IPC1-7): H03M7/14; H03M13/00
Attorney, Agent or Firm:
Hiroaki Tazawa (2 outside)