Title:
【発明の名称】2進アップ/ダウンカウンター
Document Type and Number:
Japanese Patent JP2563578
Kind Code:
B2
Abstract:
A high speed CMOS binary up/down counter (10) having a 200 MHZ clock rate comprises a 4-bit counting section that may be concatenated in multiple 4-bit sections. The counter (10) performs in an up-count mode or a down-count mode in accordance with the state of an up/down mode select signal (U/D). Each stage (11) of the 4-bit counting section comprises a propagate/kill/generate gate (28) for determining the status of a carry signal (CO) to a next stage, except the last stage of a 4-bit section, which does not require such a gate because it is coupled to a carry-forward generator (34) along with the outputs (A0,A1,A2,A3) from the other preceding stages in the section. Each 4-bit section (10) performs the counting function through a successive process of a modulo-two sums formed by modulo-2 summers (20,22,24,26) of a lower order carry and the current state of a counter stage without the need for cumbersome gating structures. The count of each stage is stored in a D-type flip-flop (12,14,16,18). The Q or Q output of the flip-flop is selected by a selector (40,42,44,46) to provide the current state of the stage to the summer (20,22,24,26) in dependence upon the mode select signal (U/D).
Inventors:
EDOWAADO TEII RUISU
Application Number:
JP13445889A
Publication Date:
December 11, 1996
Filing Date:
May 26, 1989
Export Citation:
Assignee:
RAYTHEON CO
International Classes:
G06F7/62; H03K3/037; H03K3/356; H03K23/00; H03K23/52; H03K23/56; (IPC1-7): H03K23/56; G06F7/62
Domestic Patent References:
| JP6084015A | ||||
| JP5227348A | ||||
| JP6124330A | ||||
| JP6010922A | ||||
| JP59221031A | ||||
| JP62151023A |
Other References:
【文献】 米国特許3943378(US,A)
【文献】 米国特許4037085(US,A)
【文献】 米国特許4611337(US,A)
【文献】 米国特許4037085(US,A)
【文献】 米国特許4611337(US,A)
Attorney, Agent or Firm:
Kyozo Yuasa (4 outside)