Title:
【発明の名称】ブロックIIRプロセッサ
Document Type and Number:
Japanese Patent JP3092534
Kind Code:
B2
Abstract:
A block infinite impulse response (IIR) processor has a first input register storing data of the block length "L" and capable of shifting the stored data by an integer times the data word length, a first coefficient register file, a second input register, a second coefficient register file, a third input register, a third coefficient register file, a register, a shift register, an accumulator and a multiply-and-accumulate unit for multiplying respective data blocks in the register by a least significant word in the shift register, and for adding the result of the multiplication to a value of the accumulator, for executing a parallel operation of "L" multiply-and-accumulate operations. Thus, by adopting the block IIR filter algorithm which makes it possible to simultaneously calculate a plurality of samples in a processor having a divided-ALU instructions for executing a plurality of multiply-and-accumulate operations in parallel to one another, the filter operation can be speeded up by use of the parallel arithmetic operation. The operation can be also speeded up by reducing the number of multiply-and-accumulate operations in accordance with the order of the filter because of the nature of coefficients.
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Inventors:
Ichiro Kuroda
Application Number:
JP35266896A
Publication Date:
September 25, 2000
Filing Date:
December 13, 1996
Export Citation:
Assignee:
NEC
International Classes:
H03H17/04; G06F17/10; G06T1/20; (IPC1-7): G06F17/10; H03H17/04
Domestic Patent References:
| JP944472A |
Attorney, Agent or Firm:
Asamichi Kato