SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF

Title:

SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF

Document Type and Number:

Japanese Patent JPH0629288

Kind Code:

A

Abstract:

PURPOSE: To remove contact failures, leakage current or the like and eliminate any need to increase the width of a poly-silicon layer at a portion of a connection hole.

CONSTITUTION: When connecting a semiconductor substrate 100 to a wiring layer, a silicide layer 201 is designed to be present in an opening section 105 even when a silicon layer 103 is deviated from the opening section 105 so that a 10: 1 etching selection ratio may be available between the polysilicon layer 103 and the silicide layer 201, which prevents a silicon substrate in an active area of devices from being etched. As a result, no active area 101 of the devices will be removed by the etching. Furthermore, there is no need to increase the width of the polysilicon layer in the opening section 105. It is, therefore, possible to reduce a chip area by about 30% in the case of a mask ROM of 6 megabits.

Inventors:

TANAKA KAZUO

Application Number:

JP18355492A

Publication Date:

February 04, 1994

Filing Date:

July 10, 1992

Export Citation:

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Assignee:

SEIKO EPSON CORP

International Classes:

H01L21/28; H01L21/302; H01L21/3065; H01L21/3205; H01L23/52; (IPC1-7): H01L21/3205; H01L21/28; H01L21/302

Attorney, Agent or Firm:

Kisaburo Suzuki (1 outside)

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