Title:
【発明の名称】クロツクパルス発生装置
Document Type and Number:
Japanese Patent JPS5925401
Kind Code:
B2
Abstract:
1535231 Pulse oscillator circuits PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 18 Feb 1976 [21 Feb 1975] 06372/76 Heading H3T In a self-triggered pulse oscillator circuit including a single non-inverting logic gate 12 and an oscillator element such as crystal 15 connected as a series resonator between the output and input of the gate the element 15 is constructed so that a phase difference of less than 45 degrees occurs in operation between signals at its input and output terminals, an output 22 of a circuit loop containing the gate and the element is connected to an input of a second logic gate 13 and the output of gate 13 is connected via an integrating network 18, 19 to the non-inverting logic gate for setting the relationship between the standing level at its input and its transfer characteristic so that the standing level lies in the centre of the logic changeover region of the characteristic. The oscillator includes a Schottky AND gate 12 and a NAND gate 13 and oscillation can be stopped by appropriate signals to 20, 21. Output can be from 38 via a delay element and inverting gates 36, 37 and also from 34. In a further embodiment (Fig. 3, not shown) a capacitor (23) in parallel with the crystal 15 short circuits higher harmonics than the required fundamental or e.g. third harmonic output (30, 31) from NAND gates (24, 25). Oscillation can be stopped by appropriate input at (29) to block gate 13. Schottky TTL gates or ECL gates can be used. The oscillator can be used to generate clock pulses.
Inventors:
RUDEI DEIRUKU ANTONII SHORUTEN
ANTONIUSU HERARUDESU BITSUSERU
ANTONIUSU HERARUDESU BITSUSERU
Application Number:
JP1605876A
Publication Date:
June 18, 1984
Filing Date:
February 18, 1976
Export Citation:
Assignee:
FUIRITSUPUSU FURUUIRANPENFUABURIKEN NV
International Classes:
H03B5/36; H03K3/027; H03K3/03; H03K3/282; H03L1/00; (IPC1-7): H03B5/36
Attorney, Agent or Firm:
Akihide Sugimura