Title:
INTER-DEVICE BUS CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS5858671
Kind Code:
A
Abstract:
PURPOSE:To make the address control of a processor having a system control function unnecessary, by setting a bit indicating the communication to a device having a control function of a system, to a transmitting address, and sending it out to an inter-device bus, at the time of said communication. CONSTITUTION:On inter-device communicating interfaces 21-91 for connecting an inter-device bus 1 and each processor 2-6, a flag A1 indicating whether a device (for instance, a device 2) having a control function of a system is connected or not is provided, and in case of communication between devices of information except control of the system, and communication to each device from the device 2, in the system control information, a logical address is designated as a transmitting destination address. Subsequently, it is converted to an absolute address by said interface, and after that, is executed through the bus 1, and communication to said device 2 from each device, in the system control information is sent out to the bus 1 by setting a bit indicating the fact that it is communication to a device having a system control function, to the transmitting address, and it is detected by a receiving origin interface.
Inventors:
TANAKA KIYOTO
FUKUOKA HIDEKI
ISHIKAWA ATSUSHI
FUKUOKA HIDEKI
ISHIKAWA ATSUSHI
Application Number:
JP15786581A
Publication Date:
April 07, 1983
Filing Date:
October 03, 1981
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
G06F13/00; G06F12/06; G06F15/16; G06F15/177; (IPC1-7): G06F3/04; G06F15/16; H04L11/00
Attorney, Agent or Firm:
Makoto Suzuki