PURPOSE: To accurately reproduce clocks without generating the pseudo pull-in of the clocks by monitoring the level of sampled reproducing signals and interrupting the circuit of a clock reproducing system when the levels of sampling signals and the delay signals are respectively zero level.

CONSTITUTION: The sampling signal Yn and a signal Yn-1 delayed for one symbol from the sampling signal are compared at a comparator 24 and when it is discriminated that the both signals are turned to the zero level simultaneously, an opening/closing switch 80 provided between a subtractor 67 and a loop filter 68 is opened by a zero level monitoring circuit 10. Thus, the input of a phase difference Zn detected at the subtractor 67 to the loop filter 68 is interrupted, a voltage controlled oscillator 69 is self-driven and there is no possibility of the clock being reproduced by pseudo pull-in. Then, when an oscillation frequency arrives near a normal clock frequency, the levels of the sampling signal Yn and the delay signal Yn-1 are not the zero level so that the switch 80 is closed by the circuit 10 and the clock is pulled in.