Title:
【発明の名称】カウンタ回路
Document Type and Number:
Japanese Patent JP2520962
Kind Code:
B2
Abstract:
A high speed counter circuit for counting electrical pulses includes a master/slave flip-flop at the input stage of the counter. An AND gate logically ANDs the pulses being counted with the master output to produce a first gating signal. A plurality of cascade coupled flip-flops each having a slave and an inverse slave output are provided. The clock input to each cascade coupled flip-flop is produced by the logical OR of the electrical pulses being counted, the first gating signal and the slave output of all preceding flip-flops of the counter. The counter output is provided by the inverse slave output of each flip-flop.
Inventors:
ROORENSU JOSEFU KURAASO
DEIRU YUUJIN HOFUMAN
KYAROORU YUUJIN MOOGAN
CHAARUZU ARUBAATO PANTAA
DEIIN KEI YANGU
DEIRU YUUJIN HOFUMAN
KYAROORU YUUJIN MOOGAN
CHAARUZU ARUBAATO PANTAA
DEIIN KEI YANGU
Application Number:
JP20710989A
Publication Date:
July 31, 1996
Filing Date:
August 11, 1989
Export Citation:
Assignee:
INTAANASHONARU BIJINESU MASHIINZU CORP
International Classes:
H03K23/00; H03K3/037; H03K23/40; H03K23/50; (IPC1-7): H03K23/50
Domestic Patent References:
| JP1157616A | ||||
| JP62198219A |
Attorney, Agent or Firm:
Kiyoshi Goda (2 outside)