Title:
【発明の名称】カウンタ回路
Document Type and Number:
Japanese Patent JP2569589
Kind Code:
B2
Abstract:
Disclosed is a combination of a counter operating in response to an input signal, a latch circuit for latching the output of the counter and a read-command signal inhibiting circuit controlling the latch circuit so as not to effect the latch operation for a predetermined period from the input signal for a time necessary for the operation of the counter, in response to a read-command signal.
Inventors:
Kochika Masako
Application Number:
JP21561687A
Publication Date:
January 08, 1997
Filing Date:
August 28, 1987
Export Citation:
Assignee:
NEC
International Classes:
H03K21/08; H03K5/26; H03K21/02; H03K21/12; H03K23/86; (IPC1-7): H03K23/86; H03K21/08
Domestic Patent References:
| JP57194636A | ||||
| JP5754432A | ||||
| JP6051026A | ||||
| JP62173819A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)