【発明の名称】計数回路

Japanese Patent JPH0758905

B2

Counter circuit apparatus which sequentially re-allocates lower-order counting operation in order to extend counter life. The counter is comprised of a plurality of lower order counters and at least one higher order counter. A count selection circuit is coupled to the plurality of counters which controls the counting thereof in response to applied event input signals. A map control circuit is coupled between the higher order counter and the count selection circuit which controls the count selection circuit in response to signals derived from the higher order counter. The map control circuit sequentially enables a predetermined one of the lower order counters to count individual ones of the applied event input signals. A count unscrambling circuit is coupled to the plurality of lower order counters and the map control circuit which produces an ordered count output signal that is indicative of the number of event input signals counted by the counter. The operating lifetime of the counters is increased utilizing the principles of the present invention. One application of the present invention is that of a non-volatile up counter suitable for an odometer application. A counting method which provides for extended counter life is also disclosed.

Yoshiaki Sasaki
Fukuda Noriaki

JP4013886A

June 21, 1995

February 25, 1986

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Kenerum Deigby Murray

H03K23/50; H03K21/00; H03K21/40; (IPC1-7): H03K23/50

Ishihara Masanori

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