Title:
【発明の名称】デ-タソ-スシステム
Document Type and Number:
Japanese Patent JPH0754466
Kind Code:
B2
Abstract:
The invention relates to data source systems including digital circuits such as processors or control units in which a number of data lines are controlled in dependence of the position of a counter. A data source circuit of the system allows for several data lines to be simultaneously controlled by means of a comparison register and a comparator in that a given logic state is stored in a qualification unit, said logic state controlling the data lines when the counter position is reached ( via an output register). This offers the advantage that several components, for example the bus connection means of a processor, become independent of the control of these data lines and hence remain available for other functions.
Inventors:
Efeld Dirk van Felduizen
Application Number:
JP9662486A
Publication Date:
June 07, 1995
Filing Date:
April 25, 1986
Export Citation:
Assignee:
N-Filippus Full-Iran Penhu Abriken
International Classes:
G05B19/042; G06F1/04; G06F1/14; G06F9/48; G06F9/46; H03K23/66; (IPC1-7): G06F9/46; G06F1/14
Domestic Patent References:
| JP5699528A | ||||
| JP5248924A | ||||
| JP54151345A |
Attorney, Agent or Firm:
Akihide Sugimura (1 outside)
Next Patent: データ処理装置