PURPOSE: To avoid the erroneous reproduction caused by the disturbance of a synchronizing signal regardless of a high signal frequency, by deciding the erroneous sampling due to a peak shift by making use of a 3-phase synchronizing signal and producing a compensated sampling pulse.

CONSTITUTION: The input information of one side is applied to a phase detector 1, and the 3-phase synchronizing signals (eWg) are produced from a delaying circuit 6. Then the signal (e) is fed back to the detector 1. The output of the detector 1 is latched by a latching circuit 8 controlled by the signal (f) via a storage circuit 4 and then compared with the next storage contents of the circuit 4 through a comparator 7 which is controlled by the signal (e). When a new input is ≤1/n the previous storage contents, an error signal is produced. Then the signal (f) is substantially erased via a window circuit 9 controlled by the signal (g) and an AND gate 11. Thus a sampling compensating pulse is produced from a compensating circuit 13 controlled by the signal (g) and synchronously with the next signal (e). As a result, the erroneous sampling due to a peak shift is avoided regardless of a high frequency. Thus the erroneous reproduction is prevented for the information.