PURPOSE: To keep dispersion of threshold value voltage of a memory transistor caused by emitting operation of electrons, for example, erasing operation within appropriate range and to make erasing time optimum.

CONSTITUTION: Erasing operation is performed by impressing the prescribed potential difference between control gate electrodes and source electrodes of memory transistors 1a-1d by a potential difference setting section 30. Also, verifying operation can be performed by detecting threshold value voltage of the memory transistors 1a-1d. In this case, the potential difference setting section 30 controls impressing time for potential difference or magnitude of potential difference based on a DETECT signal from a verifying circuit 8, that is, in accordance with threshold value voltage of the memory transistor. Thereby, over erasing can be efficiently prevented, while erasing time can be made optimum.