Title:
【発明の名称】デコーダ回路
Document Type and Number:
Japanese Patent JP2940175
Kind Code:
B2
Abstract:
PURPOSE:To eliminate the possibility of breakdown of insulation and to allow the high-speed driving of word lines by forming the word line driving transistors formed in N wells to a channel type and supplying the bias signals different from clock signals for writing into the N wells. CONSTITUTION:The word line driving transistors Q0, Q1... of the P channel type are formed within the N well NW1. The other bias signal phi2 is supplied without using the signal phi1 for driving word lines in order to bias the N well NW1 to a high-voltage stage. The need for increasing the gate voltage of the TRs Q0... is eliminated in this way even if the voltage of the word lines is increased in order to allow the sure writing. The load of the signal phi1 is decreased and the word line driving is speeded up.
Inventors:
MUROTANI KITOKU
Application Number:
JP2189791A
Publication Date:
August 25, 1999
Filing Date:
February 15, 1991
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G11C11/413; G11C11/407; G11C16/06; G11C17/00; G11C17/12; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): H01L27/108; G11C11/407; G11C11/413; G11C16/06; G11C17/12; H01L21/8242
Domestic Patent References:
| JP3246962A | ||||
| JP63275157A |
Other References:
ＩＥＥＥ ＪＯＵＲＮＡＬ ＯＦ ＳＯＬＩＤ−ＳＴＡＴＥ ＣＩＲＣＵＩＴＳ，２４［５］（１９８９）ｐｐ．１１７０−１１７５
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)