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Title:
POWER-DOWN MONITOR CIRCUIT
Document Type and Number:
Japanese Patent JPS5919299
Kind Code:
A
Abstract:

PURPOSE: To obtain a detection output with high reliability, by detecting whether or not a power supply voltag is decreased from a margin voltage having a good relative accuracy to a memory cell holding voltage of a static RAM circuit.

CONSTITUTION: In figure, 30 is a memory cell of a static RAM circuit and a flip-flop circuit 34 of the same connection is constituted and the relation of the size of each transistor (TR) is set as T1'>T2'=T1=T2, T3'<T4'T3=T4. Thus, the holding voltage of a power-down write data is increased slightly (α) higher than that of the memory cell 30 in the flip-flop circuit 34 because of the unbalance of the potential of nodes A and B. Thus, when a standby power supply voltage VSB is lower than the data holding voltage of the memory cell 30 having a margin voltage α, the TRT5 is inverted off, the node A is inverted to the high level and the TRT4' is inverted on, the node B is inverted to the low level, allowing to attain the detection of power-down.


Inventors:
HIRAHARA JIROU
Application Number:
JP12712182A
Publication Date:
January 31, 1984
Filing Date:
July 21, 1982
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
G06F12/16; G06F1/26; G06F1/28; G11C29/50; (IPC1-7): G06F1/00; G11C29/00
Attorney, Agent or Firm:
Takehiko Suzue