Title:
TRANSMISSION SYSTEM
Document Type and Number:
Japanese Patent JPH0779210
Kind Code:
A
Abstract:
PURPOSE: To reproduce phase transition by synthesizing a correction value generated from a phase difference between low and high order VCs and a differential value. CONSTITUTION: Reading from a buffer storage 5 is controlled by a reading address generator 10 and a clock signal is supplied from a reading clock signal generator 11 formed by a controller and a final control element to the generator 10. Addresses from a writing address generator 8 and the generator 10 are supplied to a differential circuit 12 from which a differential value is supplied to a mean value memory 13. The memory 13 averages the differential value. A correction value from a correction circuit 9 and the differential value from the memory 13 are supplied to a synthetic circuit 14 and a synthetic value is supplied to the generator 11. Only when the generator 11 is driven at a low reading clock speed, the memory 13 is required and the clock signal is averaged by the generator 11. The circuit 9 includes a correction table for correcting the mean value of the memory 13. Thus phase transition which is not generated by the transition of delays can be almost completely reproduced by a desynchronized signal.
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Inventors:
RARUFU URUBANSUKII
Application Number:
JP18834994A
Publication Date:
March 20, 1995
Filing Date:
August 10, 1994
Export Citation:
Assignee:
PHILIPS ELECTRONICS NV
International Classes:
H04J3/00; H04J3/07; H04L7/00; (IPC1-7): H04J3/07; H04L7/00
Attorney, Agent or Firm:
Akihide Sugimura (5 outside)
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