Title:
【発明の名称】デジタルプログラマブル高速度周波数分割器
Document Type and Number:
Japanese Patent JPH03502753
Kind Code:
A
Abstract:
A high speed digital programmable frequency divider (100) capable of frequency division by even and odd integers is disclosed herein. The frequency divider (100) of the present invention includes a waveform generator (200) for providing a periodic input waveform of a first period and the inverse thereof. The present invention further includes a clocked ring oscillator circuit (400) for providing first and second closed signal paths, in response to the input waveform, disposed to invert signals passing therethrough. The first and second signal paths have a common output node (499) and first and second propagation delays substantially equal to first and second integral multiples of the first period, respectively. In addition, the frequency divider (100) includes a programmable switch network (500) for opening the first and second signal paths to provide a periodic output waveform at the output node (499).
Inventors:
Lawrence Yee, Larson
Application Number:
JP51035289A
Publication Date:
June 20, 1991
Filing Date:
August 28, 1989
Export Citation:
Assignee:
HIUSE Aircraft Company
International Classes:
H03K23/44; H03K23/54; H03K21/00; H03K23/66; (IPC1-7): H03K21/00; H03K23/54
Attorney, Agent or Firm:
Takehiko Suzue (3 outside)