Title:
【発明の名称】分周回路
Document Type and Number:
Japanese Patent JPH0683065
Kind Code:
B2
Abstract:
In a frequency-dividing circuit for producing an output having a frequency half that of its input, a pair of terminals of a latch circuit (20) are connected to input terminals of a pair of delay means (31,32), and are also connected to receive through a pair of transistors (11,12), the outputs of the delay means. A single-phase input signal (CK) is input to the control electrodes of the transistors to turn on and off the transistors. When the transistors are turned from off to on, the output states of the delay means are transferred through the transistors to invert the latch circuit, and the states of complementary terminals of the latch circuits are in turn transferred through the delay means to invert the output states of the outputs of the delay means. When the transistors are turned from on to off, no change occurs in the states of the circuit. In this way, the states of the circuit are inverted each time the transistors are turned from off to on. A frequency-divided output can therefore be derived at one of the outputs of the first and second delay means. Either one or both of the first and second inverters (21,22) may be replaced by a NAND gate or a NOR gate for permitting reset of the circuit.
Inventors:
TANAKA KOTARO
YOMO MAKOTO
AKYAMA MASAHIRO
YOMO MAKOTO
AKYAMA MASAHIRO
Application Number:
JP2847588A
Publication Date:
October 19, 1994
Filing Date:
February 09, 1988
Export Citation:
Assignee:
OKI ELECTRIC IND CO LTD
International Classes:
H03K23/44; H03K3/037; H03K23/00; (IPC1-7): H03K23/00; H03K23/44
Attorney, Agent or Firm:
Kakimoto Kyosei