PURPOSE: To provide a master slice type LSI basic cell which can be applied to a high speed gate and a high density memory.
CONSTITUTION: A P-MOS transistor and an N-MOS transistor whose sizes are approximately a half the MOS channel width necessary to obtain a required gate speed are provided to compose one set. Two such sets (14 and 15) and (16 and 17) are arranged in the direction of their gate electrodes. Four memory N-MOS transistors 18, 19, 28 and 29 whose sizes are approximately a half the channel widths of these MOS transistors are provided on both ends of the electrode directions of those MOS transistors. Two gate circuits composed of two sets of the P-MOS transistors and the N-MOS transistors whose sizes are approximately a half the MOS channel width necessary to obtain the required gate speed are provided in parallel with each other to constitute a gate circuit part from which an output is supplied to a wiring channel.
HORINO NOZOMI
KAMINAGA YASUO
KOBAYASHI YUTAKA
