Title:
【発明の名称】ECL分周回路
Document Type and Number:
Japanese Patent JP2536222
Kind Code:
B2
Abstract:
PURPOSE:To suppress self-oscillation specific to a frequency dividing circuit while the difference of an input DC offset current is minimized by selecting the size of the emitter of a transistor(TR) through which a current for a slave amplifier is supplied to the size of a multiple of (GO+1)/(GO-1) of the TR of a master amplifier or above. CONSTITUTION:The size of the emitter of a TR through which a current for a slave amplifier is supplied in a middle-stage input clock amplifier stage is set to the size of a TR of a master amplifier of middle-stage input clock amplifier stage as a multiple of (GO+1)/(GO-1) (GO is a DC gain of a data amplifier). Thus, the free-run operation of a frequency dividing circuit is suppressed without increasing number of components while the deterioration in the minimum input sensitivity and of the highest operating frequency characteristic is minimized.
Inventors:
ISHII HIDEKAZU
KONDO TOYOO
KONDO TOYOO
Application Number:
JP7812890A
Publication Date:
September 18, 1996
Filing Date:
March 27, 1990
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H03K3/286; H03K3/289; H03K21/40; H03K23/00; (IPC1-7): H03K23/00; H03K3/286; H03K3/289
Domestic Patent References:
| JP61237514A | ||||
| JP62243353A | ||||
| JP1284011A | ||||
| JP5344161A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)