Title:
【発明の名称】電子式郵便料金計装置
Document Type and Number:
Japanese Patent JP2532356
Kind Code:
B2
Abstract:
A memory protection circuit for a postage meter prevents the inadvertent writing of spurious data into memory locations in nonvolatile memory (62) during a power down cycle. The memory protection circuit works in conjunction with a WRITE voltage terminal associated with the nonvolatile memory (62). Means (100, 64) couple a first voltage source (78, 82, 84, 86, 88) providing a predetermined polarity voltage to the WRITE voltage terminal when a predetermined power condition exists such that the nonvolatile memory (62) is enabled to have data written into memory locations thereof. When the predetermined power condition does not exist, the means (100, 64) utilize a second different voltage source (66, 68, 72) to change the voltage level at the WRITE voltage terminal to ensure that data is not written into the memory locations.
Inventors:
ARUTON BURUTSUKUSU ETSUKAATO
Application Number:
JP17081982A
Publication Date:
September 11, 1996
Filing Date:
September 29, 1982
Export Citation:
Assignee:
PITNEY BOWES
International Classes:
G06F12/16; G07B17/00; G07B17/02; G11C7/24; G11C16/22; G11C16/30; (IPC1-7): G07B17/02; G06F12/16
Domestic Patent References:
| JP5697187A | ||||
| JP54106134A |
Attorney, Agent or Firm:
Kyozo Yuasa (3 outside)