Title:
【発明の名称】障害処理方式
Document Type and Number:
Japanese Patent JP2752764
Kind Code:
B2
Abstract:
In a high speed computer having a memory (11, 12) and a plurality of arithmetic processors divided into groups, the arithmetic processors (15) of each group being connected to the memory (11, 12) in a hierarchical order in a master-subordinate relationship, the memory and the arithmetic processors generates an alarm signal indicating a failed part of the memory (11, 12) and each of the arithmetic processors (15). During a fault recovery process, a test program is performed on the computer to determine if it is properly functioning. If a favorable result is indicated, the computer is restarted in an original system configuration. Otherwise, part of the arithmetic processors (15) is isolated from the computer depending on the alarm signal to degrade the computer into a first degraded system configuration. The test program is performed again on the first degraded system configuration. If the second test produces a favorable result, the computer is restarted in the first degraded system configuration. Otherwise, one or more of the arithmetic processors (15) are isolated from the computer depending on the alarm signal so that the computer is degraded into a second degraded system configuration.
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Inventors:
JITSUHO AKIRA
NAKAMURA AKIHIKO
NAKAMURA AKIHIKO
Application Number:
JP5861990A
Publication Date:
May 18, 1998
Filing Date:
March 08, 1990
Export Citation:
Assignee:
NIPPON DENKI KK
KOFU NIPPON DENKI KK
KOFU NIPPON DENKI KK
International Classes:
G06F11/20; G06F11/00; G06F15/16; G06F15/177; G06F17/16; G06F11/14; G06F11/22; (IPC1-7): G06F11/20; G06F15/16; G06F17/16
Domestic Patent References:
| JP60134971A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)