Title:
【発明の名称】デイジタル2導体母線データ通信システム用の故障許容出力段
Document Type and Number:
Japanese Patent JP2841182
Kind Code:
B2
Abstract:
The invention provides a fault tolerant output stage for a digital two-conductor bus data communication system of the type having a transmission module and a reception stage which contains a bus signal intermediate processing module and a reception module connected downstream that conditions incoming bus signals for a data processing unit which is connected downstream. A state detection module is connected to the bus lines to detect a short-circuit between the bus lines, in which case the transmission module can be switched over between a difference mode of operation and a single-wire mode of operation under the control of the state detection module. The intermediate processing module is configured to condition the bus signals for the reception module automatically or under the control of the state detection module, both in the case of fault free bus lines and in the case of an interruption or short-circuit to the high or low supply voltage of one of the two bus lines and in the case of a short-circuit of the two bus lines to one another.
Inventors:
YURUGEN MIIMUUTO
ORIUAA KAUFUMAN
ORIUAA KAUFUMAN
Application Number:
JP4941196A
Publication Date:
December 24, 1998
Filing Date:
February 01, 1996
Export Citation:
Assignee:
DAIMURAA BENTSU AG
International Classes:
H04L25/02; H04L12/40; H04L25/08; H04L69/40; B60R16/02; B60R16/03; (IPC1-7): H04L29/14; H04L25/02
Domestic Patent References:
| JP6244846A | ||||
| JP341841A |
Attorney, Agent or Firm:
Osamu Nakahira