PURPOSE: To decode optional restriction length and to reduce the development cost of an LSI by dividing the specific number of pass memories into the specific number of blocks and applying an initial value to the 1st-stage pass memory in each block.

CONSTITUTION: In accordance with restriction length K=N, 2N-1 pass memories 3 are divided into 2M-1 blocks, '0' and '1' are alternately applied to respective blocks as initial values to the pass memories 3 on the 1st stages of respective blocks and plural ACS circuits 200 to 2063 are similarly divided into 2N-1 blocks and controlled so that the same bus selection signal is outputted from 2N-M ACS circuits in respective blocks. Consequently the ACS circuits and pass memories 3 in each clock are similarly driven. Thereby a viterbi decoder with optional restriction length less than restriction length K=N can be attained only by one viterbi decoder.