CMOS INTEGRATED CIRCUIT

Title:

CMOS INTEGRATED CIRCUIT

Document Type and Number:

Japanese Patent JPH0758212

Kind Code:

A

Abstract:

PURPOSE: To form a positive/negative polarity high voltage circuit and a large- scale low voltage circuit on the same chip.

CONSTITUTION: A high voltage circuit 21 is composed of a CMOS circuit comprising a pMOS transistor 16 formed in the n-well 12 on an nM0S transistor 15 formed on a p-type semiconductor substrate 11, and the p-type semiconductor substrate 11. A low voltage circuit 22 is composed of a CMOS circuit comprising the pMOS transistor 18 formed in the well 13 on a p-type semiconductor 11 and the nMOS transistor 17 formed in the p-well 14 in an n-well 13.

Inventors:

OSAWA NOBUHIKO
ITO SHINICHI
ABE HIDEJI

Application Number:

JP22829893A

Publication Date:

March 03, 1995

Filing Date:

August 19, 1993

Export Citation:

Click for automatic bibliography generation Help

Assignee:

SONY CORP

International Classes:

H01L21/8238; H01L27/02; H01L27/092; H01L29/10; (IPC1-7): H01L21/8238; H01L27/092

Attorney, Agent or Firm:

Kuninori Funabashi

Next Patent: WELL FORMING METHOD IN SEMICONDUCTOR DEVICE