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Title:
CONTROL SYSTEM OF INFORMATION TRANSFER
Document Type and Number:
Japanese Patent JPS59721
Kind Code:
A
Abstract:

PURPOSE: To make data transfer processing efficient, by allowing a bus converter to perform always the transfer on the assumption that fraction data remains in a buffer.

CONSTITUTION: First, a transfer controlling circuit 18 supplies the number of an input/output device and the transfer byte position to a buffer 8 in performing data transfer from the 1st to the 2nd bus so as to shift data from a port 9 to the buffer 8. Then, the data in the buffer is transmitted to the 2nd bus. Further, when the data is tansferred from the 2nd to the 1st bus, the started input/output devivce supplies the number of the input/output device and the byte location to be stored at first and transfers the data to the buffer. Then, the data is shifted from the buffer 8 to a port 10.


Inventors:
HAIDA HIROTOSHI
WADA OSAMU
KATAKURA OSAMU
Application Number:
JP11098082A
Publication Date:
January 05, 1984
Filing Date:
June 28, 1982
Export Citation:
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Assignee:
PANA FACOM KK
International Classes:
G06F13/36; G06F13/40; (IPC1-7): G06F3/00
Domestic Patent References:
JPS5080737A1975-07-01
JPS5474640A1979-06-14
Attorney, Agent or Firm:
Fumihiro Hasegawa



 
Next Patent: JPH059722