Title:
【発明の名称】周波数シンセサイザ
Document Type and Number:
Japanese Patent JPH0763125
Kind Code:
B2
Abstract:
A saw-tooth waveform signal generating circuit 3 generates a saw-tooth waveform signal d in response to a timing signal b derived from a reference clock a. A voltage comparator 4 slices the saw-tooth waveform signal with a reference voltage to shape the waveform thereof, thereby producing a synthesizer output e having a rectangular waveform. A counter 5 adds or subtracts a predetermined value every time a reference clock arrives. The count of the counter 5 is converted to an analog value by a DAC 6 and then is applied to, for example, the saw-tooth waveform signal generating circuit as a bias. As a result, the voltage for causing the saw-tooth waveform signal to start rising or falling is manipulated to allow the voltage comparator to slice the saw-tooth waveform signal at any desired timing. Hence, a synthesizer output can be produced in any desired phase.
Inventors:
Hideo Miyashita
Uraya Shin
Uraya Shin
Application Number:
JP4859193A
Publication Date:
July 05, 1995
Filing Date:
February 15, 1993
Export Citation:
Assignee:
NEC
NEC Mobile Communications Co., Ltd.
NEC Mobile Communications Co., Ltd.
International Classes:
H03B28/00; G06F1/02; G06F7/72; G06J1/00; (IPC1-7): H03B28/00
Attorney, Agent or Firm:
Hachiman Yoshihiro
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