Title:
【発明の名称】ゲート・アレイ集積回路
Document Type and Number:
Japanese Patent JP3125996
Kind Code:
B2
Abstract:
An architecture for the input/output circuits and pads of a gate array integrated circuit product functionally configured during the formation and connection of one or more metallization layers. In a preferable practice of the invention, cells of first impurity type and second impurity type transistors are formed in respective parallel but spaced apart rows along the chip perimeters with a pad definition region lying therebetween. Successively adjacent cell transistors are contiguous as to source regions and are electrically separable by cell gate isolation. Preferably, the individual cell transistors have annular gate electrodes with centrally disposed and also fully isolatable drain regions. The input/output architecture of the present invention provides the gate array designer with the ability to selectively define pad size and spacing, to selectively utilize cells for I/O circuit functions, and to selectively isolate and cascade interconnect cell transistors to provide extended ranges of current drive and operating voltage.
Inventors:
Harold S. Crafts
Application Number:
JP14017390A
Publication Date:
January 22, 2001
Filing Date:
May 31, 1990
Export Citation:
Assignee:
Hyundai Electronics America
NC International Inc.
Symbios Logic Inc.
NC International Inc.
Symbios Logic Inc.
International Classes:
H01L21/82; H01L27/118; (IPC1-7): H01L21/82; H01L27/118
Domestic Patent References:
| JP1140835U |
Attorney, Agent or Firm:
Yoshiaki Nishiyama (2 outside)