PURPOSE: To reduce the influences of ground noises by dividing the ground side FETs constituting an input gate circuit on a chip and connecting the sources to the divided ground lines.

CONSTITUTION: Two N-channel FETN1 and N2 are formed in the symmetrical areas on a common diffusion layer formed on a chip around a common drain layer. The drain layer is connected to an output line A1. The gate layers of both FETN1 and N2 are formed in the right and left areas which are adjacent to the drain layer, and these gate layers are connected to an input signal terminal IN1. The source layer of the FETN1 is formed in the outer left area and connected to a ground pad via a ground line L1, and the source layer of the FETN2 is formed in the outer right area and connected to a ground line L2. For instance, the memory sensing circuits and the output buffer circuits are stored in both lines L1 and L2 respectively. Thus the timings when the ground noise peaks occur can be scattered.