PURPOSE: To output a ripple-free converted voltage even when a frequency is low, by generating and outputting the 2nd pulse together with change-point detection pulses regarding an input signal when the interval of the detection pulses is greater than a specific value.

CONSTITUTION: A change-point detecting circuit 103a outputs a normal rotation pulse P with a period corresponding to a number of revolution in response to the rising and falling of pulses P1 and P2 which have a π/2 frequency phase shift corresponding to rotation and the detection of a leading pulse. This pulse P triggers a monostable multivibrator 103b, but it is not reset through a transistor (TR) when the period of the pulse P is long, so the output TS of the monostable multivibrator 103b is still at a high level. Then, a signal ES delayed by FFs 103d and 103c controls a logical gate and when the period of the pulse P is long, a pulse CS delayed by the FF103c is added to the pulse P to increase the pulse width of the frequency-converted voltage outputted from an OR circuit OR2, so that even when the frequency is low, the less-rippled frequency-converted voltage is generated through an LPF, etc.