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Title:
NEURAL CIRCUIT NETWORK ADAPTIVE TO PARALLEL SYNAPSE WEIGHT ADJUSTMENT RELATED TO CORRELATIVE LEARNING ALGORITHM
Document Type and Number:
Japanese Patent JPH0620076
Kind Code:
A
Abstract:

PURPOSE: To adjust weight in real time by providing first and second floating gate devices at a semiconductor circuit.

CONSTITUTION: Each synapse cell includes a pair of floating gate devices 20 and 21 which function as a learning circuit for the parallel realization of a learning algorithm. For example, a synapse cell 25a includes floating gate devices 20a and 21b. Also, each floating gate is connected between a summary line S1 and a summary line S2, and one common floating gate member is shared. Moreover, the control gate of the floating device 20a is connected with a programming input word line 17, and the control gate of the floating gate device 21a is connected with a programming input word line 18. Then, a method for realizing weight adjustment in parallel uses a device technique for executing weight update in parallel in a prescribed number of cycles.


Inventors:
HAANAN EI KASUTORO
Application Number:
JP7507793A
Publication Date:
January 28, 1994
Filing Date:
March 10, 1993
Export Citation:
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Assignee:
INTEL CORP
International Classes:
G06G7/60; G06N3/063; G06F15/18; G06N99/00; (IPC1-7): G06G7/60; G06F15/18
Attorney, Agent or Firm:
Masaki Yamakawa



 
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