Title:
【発明の名称】高速分周回路
Document Type and Number:
Japanese Patent JPH05504875
Kind Code:
A
Abstract:
A frequency divider receives a first frequency signal and at least one clock signal of a sub-multiple of the first frequency. The first frequency signal charges a storage terminal once each first frequency cycle and the sub-multiple frequency signal discharges the storage temrinal once each sub-multiple frequency cycle. The discharged storage terminal sets the frequency divider output which is reset by the first frequency signal when the storage terminal is discharged. The sub-multiple frequency clock signal is employed to control the storage terminal instead of a feedback path from the output to increase the operating frequency of the divider.
Inventors:
Lee, Shiwe Nen
Application Number:
JP50351291A
Publication Date:
July 22, 1993
Filing Date:
December 05, 1990
Export Citation:
Assignee:
Sarnoff Corporation
International Classes:
H03K23/00; H03K23/44; (IPC1-7): H03K23/00
Attorney, Agent or Firm:
Yoshiki Hasegawa (5 others)