Title:
【発明の名称】高速プリスケーラ
Document Type and Number:
Japanese Patent JPH04503135
Kind Code:
A
Abstract:
A high speed CMOS divide by 4/5 prescaler circuit comprises first, second, third, fourth, and fifth inverter stages. When a modulas control signal is low, the prescaler operates as five clocked inverters in series having an output which is fed back to the input of the initial stage. That is, the circuit operates as a five stage clocked ring oscillator wherein only one output changes on each clock edge. When a modulas control signal is high indicating that a divide by four is desired, the counter operates as a five stage ring oscillator for seven clock edges. On the eighth edge, feed forward circuitry forces the last three stages to change states simultaneously.
Inventors:
Herold, Barry Wayne
Tahernia, Omid
Tahernia, Omid
Application Number:
JP50339690A
Publication Date:
June 04, 1992
Filing Date:
January 16, 1990
Export Citation:
Assignee:
MOTOROLA INCORPORATED
International Classes:
H03K23/00; H03K23/64; H03K23/66; (IPC1-7): H03K23/00; H03K23/64
Attorney, Agent or Firm:
Shinsuke Onuki (1 person outside)