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Title:
DIGITAL DATA RECEIVING CIRCUIT
Document Type and Number:
Japanese Patent JPS5853257
Kind Code:
A
Abstract:

PURPOSE: To receive the data which is obtained by a majority logic with a simple constitution of circuit, by providing a dividing means of the data bits.

CONSTITUTION: It is supposed that the noise is contained in the data of a signal line 451. The sampling clock of a signal line 452 samples the data of the line 451 at the fall and stores the result in a shift register of a 3-bit length. For instance, the data is set at "0" due to the noise at the 1st sampling point. As a result, the output A (signal line 453) of the 1st bit of the register 402 is "0". The data is "1" at the next sampling point, and the line 453 is set at "1". Thus "0" which is set at the shift register at the preceding sampling point emerges at the next output B. The data is kept at "1" yet at the next sampling point, and the outputs A, B and C of the register 402 are set at "1", "1" an "0" respectively. As a result, the output of logic "1" is obtained at an output 456 owing to a majority logic.


Inventors:
HITAI YUTAKA
Application Number:
JP15139681A
Publication Date:
March 29, 1983
Filing Date:
September 26, 1981
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H04L25/08; H04L25/06; (IPC1-7): H04L25/38
Attorney, Agent or Firm:
Noriyuki Noriyuki



 
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