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Patent Searching and Data


Title:
CELL DELAY ADDING CIRCUIT
Document Type and Number:
Japanese Patent JPH0630023
Kind Code:
A
Abstract:

PURPOSE: To easily add an optional delay to each input cell for a communication equipment for an asynchronous transfer mode.

CONSTITUTION: A time stamp ts is calculated to an input cell from the sum of the delay value dy to be added and acquired from a delay value generating circuit 1 and the present time tm obtained from a clock circuit 2. Then the time stamp ts and the input cell are written in a cell buffer 4. At the reading side, a comparator 5 reads a time stamp ts' out of the buffer 4. Then a cell output-enable signal cs is outputted when the time tm exceeds the time stamp ts', and a cell is outputted from the buffer 4.


Inventors:
NAGAI TETSUYA
YAMAZAKI KATSUYUKI
Application Number:
JP18398592A
Publication Date:
February 04, 1994
Filing Date:
July 10, 1992
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
KOKUSAI DENSHIN DENWA CO LTD
International Classes:
H04L47/43; H04L47/56; H04Q3/00; H04Q11/04; (IPC1-7): H04L12/48
Attorney, Agent or Firm:
Masahiro Kurai