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Title:
MEMORY REFERENCE SYSTEM
Document Type and Number:
Japanese Patent JPS5853076
Kind Code:
A
Abstract:

PURPOSE: To prevent change in the content of a control memory, by providing a signal line transmitting a write inhibition signal to a control memory and a gate controlling the transmission of a write pulse with the write inhibition signal between a service processor and a host computer.

CONSTITUTION: In a controller 8 of a replacement memory 7, a read line controller 14 controls readout/write with an instruction from an instruction processing section 6. When a write instruction comes, the controller 14 starts a write pulse generator 15 to produce a write pulse, which is given to a gate 16. The gate 16 is provided with a write inhibition signal line to which a write inhibition signal iNHW is inputted. The gate is opened with "0" and closed with "1" to control the transmission of write pulse. Thus, the memory can be referenced without increasing an amount of the hardware and changing the content of the control memory.


Inventors:
AIZAWA TERUO
ETSUNO MINORU
Application Number:
JP15104981A
Publication Date:
March 29, 1983
Filing Date:
September 24, 1981
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F11/28; G06F12/10; G06F12/14; G06F12/16; G06F21/60; (IPC1-7): G06F13/00; G11C9/06; G11C29/00
Attorney, Agent or Firm:
Kyotani Shiro



 
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