PURPOSE: To give an optional and accurate delay to a front edge of an input signal by providing a counter whose operation is stopped until the next input signal comes when the count value reaches a prescribed counter value and a gate circuit ANDing a count stop signal and the input signal and outputting the result.

CONSTITUTION: A reset input terminal RESET of a counter circuit 11 is connected to a signal input terminal 3a via an inverter 12, and when a high level signal is applied to the terminal RESET, the resetting is released. Further, a clock input terminal CLOCK of the circuit 11 is connected to a clock input terminal 3c via AND circuits 13, 14, the circuit 13 uses an input signal as a gate signal and the circuit 14 uses a signal inverting an output at a Q6 output terminal of the circuit 11 by an inverter 15 as a gate signal respectively. Further, the Q6 terminal of the circuit 11 is connected to an input terminal of an AND circuit 16 together with the signal input terminal 3a, and a input signal to the delay circuit 3, e.g., a gas detection signal and the signal at the Q6 terminal of the circuit 11 are operated logically by the circuit 16 and its result is fed to an input terminal 3b.