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Title:
【発明の名称】集積CMOS回路
Document Type and Number:
Japanese Patent JPH11515149
Kind Code:
A
Abstract:
PCT No. PCT/EP96/04686 Sec. 371 Date Apr. 27, 1998 Sec. 102(e) Date Apr. 27, 1998 PCT Filed Oct. 28, 1996 PCT Pub. No. WO97/15952 PCT Pub. Date May 1, 1997A CMOS circuit (10), which is integrated in a semiconductor substrate, comprises a principal circuit part (12), which includes the major part of the circuit components in a well isolated from the substrate by a substrate diode. The CMOS circuit furthermore comprises a power output stage (16) driving an inductive load (26, 28). A sensor (18) is connected with one output (22, 24) of the power output stage (16) and on detection of a voltage biasing the substrate diode (30, 32) in the conducting direction produces a switching signal at the output. On occurrence of the switching signal produced by the sensor (18) a controllable switch (20) disconnects the supply voltage from the principal circuit part (12). In its own separate well (46) a status memory (14) is formed on the substrate adjacent to the principal circuit part (12), such status memory (14) comprising memory elements for storage of status data of the principal circuit part (12) on disconnection of the supply voltage.

Inventors:
Scones, kevin
Heinecke, Gunter
Buyer, Erich
Application Number:
JP51630297A
Publication Date:
December 21, 1999
Filing Date:
October 28, 1996
Export Citation:
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Assignee:
Texas Instruments Deutschland Gesellschaft Mitt Beschlenktel Haftung
International Classes:
H01L27/088; H01L21/8234; H01L27/092; H03K17/08; H03K17/695; (IPC1-7): H03K17/695; H01L21/8234; H01L27/088; H03K17/08
Attorney, Agent or Firm:
Akira Asamura (3 outside)