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Patent Searching and Data


Title:
NEGATIVE FEEDBACK AMPLIFYING CIRCUIT
Document Type and Number:
Japanese Patent JPS5821905
Kind Code:
A
Abstract:

PURPOSE: To eliminate the DC output offset voltage and to improve the DC stability, by providing an FET in parallel to another FET of a cascode amplifying circuit comprising said FET and a transistor and then applying the negative feedback to the above-mentioned FET from the transistor.

CONSTITUTION: For a cascode amplifying circuit, an FET3 is cascode-connected to a transistor TR6 and the drain voltage is decided by the voltage of a power supply 7. An FET11 which eliminates the DC offset voltage is connected in parallel to the FET3, and the drain of the FET11 is connected to a constant current source 5. While the gate of the FET11 is grounded via a capacitor 13, and at the same time the collector of the TR6 is connected to a constant current source 8 via a resistance 14.


Inventors:
FUKUDA RIYUUICHI
Application Number:
JP12110681A
Publication Date:
February 09, 1983
Filing Date:
August 01, 1981
Export Citation:
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Assignee:
NIPPON COLUMBIA
International Classes:
H03F1/22; H03F3/20; H03F3/30; H03F3/34; (IPC1-7): H03F1/22
Attorney, Agent or Firm:
Hidekuma Matsukuma