PURPOSE: To reduce the delay time of quotient generation by parallelly executing division at a low base within the time for the multiple generation of a divisor before the start of division in the case of division with high base subtraction shift type divider technique.

CONSTITUTION: The multiple of '3' is generated by a '3' multiple generation block 14 for the divisor parallelly with the division of a base 2 due to a division block 11 for the base 2, and a multiple 103 of '3', partial remainder R(1) and quotient q(1) required for the division of a base 4 are generated. Next, the multiples of '5' and '7' are generated by a 5 and 7 multiple generation block 15 for the divisor parallelly with the division of the base 4 due to a division block 12 for the base 4, and a multiple 105 of '5', multiple 106 of '7' of the divisor, partial remainder R(2) and quotients q(2) and q(3) are calculated. Afterwards, a base 8 is repeatedly divided by a division block 13 for the base 8 while using the multiples of '3', '5' and '7' of the divisor. Before the division at the base 8 is started, the multiple required for the division is generated parallelly with the generation of high-order 3 bits in the quotient.